Title:
16-1 | Polarization Enhanced GaN Complementary Logic Circuits with Short Propagation Delay
Description:
Authors: Teng Li, School of Integrated Circuits, Peking University, Beijing, China, College of Microelectronics, Beijing University of Technology, Beijing, China|Jin Wei, School of Integrated Circuits, Peking University, Beijing, China|Meng Zhang, College of Microelectronics, Beijing University of Technology, Beijing, China|Jingjing Yu, School of Integrated Circuits, Peking University, Beijing, China|Yunhong Lao, School of Integrated Circuits, Peking University, Beijing, China|Sihang Liu, School of Integrated Circuits, Peking University, Beijing, China|Ming Zhong, School of Integrated Circuits, Peking University, Beijing, China|Jiawei Cui, School of Integrated Circuits, Peking University, Beijing, China|Junjie Yang, School of Integrated Circuits, Peking University, Beijing, China|Han Yang, School of Physics, Peking University, Beijing, China|Xuelin Yang, School of Physics, Peking University, Beijing, China|Zheyang Zheng, School of Microelectronics, University of Science and Technology of China, Hefei, China|Maojun Wang, School of Integrated Circuits, Peking University, Beijing, China|Kevin J. Chen, Dept. of ECE, Hong Kong University of Science and Technology, Hong Kong, China|Bo Shen, School of Physics, Peking University, Beijing, China
In this work, we develop a GaN complementary logic IC platform. Utilizing polarization enhanced acceptor ionization, a high-performance E-mode GaN p-FET with high Imax of 23mA/mm is demonstrated. The elementary logic gate circuits are demonstrated, including GaN CL inverter, transmission, NAND, NOR gate, and RS latch. The GaN CL inverter achieves a large voltage gain of 118.9V/V. The monolithic integration of GaN power HEMT with GaN CL buffers are also presented. The GaN ring oscillators (ROs) exhibit a short average propagation delay per stage (τpd) of ~13 ns.
Type:
Technical Session