Tuesday, December 10 • 2:20 PM - 2:45 PM PST
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Location: Grand Ballroom A
Title: 20-1 | Reliable memory operation with low read disturb rate in the world smallest 1Selector-1MTJ cell for 64 Gb cross-point MRAM
Description:
Authors: Hisanori Aikawa, Kioxia Korea Corporation|Jeonghwan Song, SK hynix|Toshihiko Nagase, Kioxia Korea Corporation|Soo Man Seo, SK hynix|Yuichi Ito, Kioxia Korea Corporation|Tae Jung Ha, SK hynix|Kenichi Yoshino, Kioxia Korea Corporation|Bo Kyung Jung, SK hynix|Tadaaki Oikawa, Kioxia Korea Corporation|Ku Youl Jung, SK hynix|Su Jin Chae, SK hynix|Bum Su Kim, SK hynix|Min Chul Shin, SK hynix|Dong Keun Kim, SK hynix|Tae Ho Kim, SK hynix|Kosuke Hatsuda, Kioxia Corporation| Katsuhiko Hoya, Kioxia Corporation|Soo Gil Kim, SK hynix|Jae Yun Yi, SK hynix|Seon Yong Cha, SK hynix
For the first time, we demonstrate reliable 1 selector-1 MTJ (1S1M) cell read/write operation with low read disturb rate of <1E-6 in 64 Gb cross-point array architecture. We have implemented cross-point 1S1M chips integrated in Half Pitch (HP) of 20.5 nm and MTJ CD of 20 nm using As-doped SiO2 selector and perpendicularly magnetized MTJ (p-MTJ). A novel read scheme utilizing transient behavior of selector along with the low capacitance circuitry enables us to overcome MTJ read disturb easily occurred when the selector turns on in scaled 1S1M cells.
Type: Technical Session
Tuesday, December 10, 2024 - 02:15 PM
20 | MT | Selector Based and Charge-trap Based Memories
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