30 | MT | Ferroelectric FET and NAND Flash Memories

Event Time

Originally Aired - Wednesday, December 11 9:00 AM - 12:00 PM PST

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Event Location

Location: Grand Ballroom A


Event Information

Title: 30 | MT | Ferroelectric FET and NAND Flash Memories

Description:

This session includes 4 papers on the topic of NAND Flash and 2 papers about FeFET memories. The first paper proposes a 3D NAND Flash architecture with horizontal channel that provides superior scalability. The next 2 papers explore the use of ferroelectric layers for next generation 3D NAND memory. One paper investigates the use of oxide semiconductor channels in ferroelectric VNAND. The last two papers present results on high-endurance FeFET memories.

Type: Technical Session


Presentations

Wednesday, December 11, 2024 - 09:00 AM
30-0 | Welcome

Wednesday, December 11, 2024 - 09:05 AM
30-1 | Superior Scalability of  Advanced Horizontal Channel Flash For Future Generations of 3D Flash Memory

Wednesday, December 11, 2024 - 09:30 AM
30-2 | Gate-stack Optimization to Mitigate the Cylindrical Effect in Ferroelectric VNAND

Wednesday, December 11, 2024 - 09:55 AM
30-3 | Clarifying the Role of Ferroelectric in Expanding the Memory Window of Ferroelectric FETs with Gate-Side Injection: Isolating Contributions from Polarization and Charge Trapping

Wednesday, December 11, 2024 - 10:45 AM
30-4 | Oxide Channel Ferroelectric NAND Device with Source- tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 years) and Disturbance Immunity (△Vth ≤ 0.1 V) for QLC Operation

Wednesday, December 11, 2024 - 11:10 AM
30-5 | Novel Design Strategy for High-Endurance (>1010) and Fast-Erase Oxide-Semiconductor Channel FeFET

Wednesday, December 11, 2024 - 11:35 AM
30-6 | Demonstration of Ferroelectric FET Memory with Oxide Semiconductor Channel to Achieve Smallest Cell Area 0.009 μm2 and High Endurance for Non-Volatile High-Bandwidth Memory Applications


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