37 | MT | Materials and Process Advances for Ferroelectric Memory Applications

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Originally Aired - Wednesday, December 11 1:30 PM - 4:30 PM PST

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Event Location

Location: Grand Ballroom A


Event Information

Title: 37 | MT | Materials and Process Advances for Ferroelectric Memory Applications

Description:

This session contains 6 papers and will cover recent advances in HfO2-based ferroelectric materials optimization strategies for memory applications. In the first paper by Pohang University of Science and Technology (POSTECH), Hwang et al. demonstrated high-performance HZO-based ferroelectric capacitors with vertically well-ordered domain structures by inserting a ultra-thin 2D-WS2 bottom interfacial layer. The second paper (by KAIST and Samsung R&D) provided a new design methodology for FeRAM cell capacitor that operates at low voltage (≤ 1 V) with steep polarization (∆P) switching characteristics and overcomes disturbance issue with AFE domain engineering. The third paper (by S. Cao et al.) focused on the development of cross-point FeRAM and comprehensively investigated its application for embedded and standalone memories. The fourth paper from KAIST demonstrated 32 Kb ferroelectric random access memory array using 3D trench ferroelectric capacitor with great uniformity and excellent high temperature retention characteristics for over 10 years at 175 ℃. The last two papers, both by imec, showcased the use of IGZO in combination with ferroelectric materials to demonstrated new and improved memory applications, including an enlarged capacitive memory window (CMW) in FeCAPs (by S. Mukherjee et al.) and a novel 3D Charge Coupled Device (CCD) for high density block addressable buffer memory (by R. Kishore et al.)

Type: Technical Session


Presentations

Wednesday, December 11, 2024 - 01:30 PM
37-0 | Welcome

Wednesday, December 11, 2024 - 01:35 PM
37-1 | Record Endurance (> 1012 cycles), High Polarization (2Pr > 50 μC/cm2), and 10-year Data Retention (85 oC) in HZO Capacitors with Well-Ordered Ferroelectric Domain Structures via 2D-WS2 Interface

Wednesday, December 11, 2024 - 02:00 PM
37-2 | Design Methodology for Low-Voltage Operational (≤1 V) FRAM Cell Capacitors and Approaches for Overcoming Disturb Issues in 1T-nC Arrays: Experimental & Modeling

Wednesday, December 11, 2024 - 02:25 PM
37-3 | Comprehensive Performance Re-assessment of Hafnia-based Cross-point FeRAM with Ultra-fast and Low-power Operation from Device/Array Perspective

Wednesday, December 11, 2024 - 03:15 PM
37-4 | 3D trench Hf0.5Zr0.5O2-based 32 Kbit 1T1C FeRAM Chip with 2/5 ns Write/Read speed, Low power consumption (0.605 pJ/bit) and Prominent High-temperature Reliability (baking @ 175℃)

Wednesday, December 11, 2024 - 03:40 PM
37-5 | Improved Capacitive Memory Window for Non-destructive Read in HZO-based Ferroelectric Capacitors with Incorporation of Semiconducting IGZO

Wednesday, December 11, 2024 - 04:05 PM
37-6 | Novel High Density 3D Buffer Memory Enabled by IGZO Channel Charge Coupled Device


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